The present invention relates to a method for testing an H-bridge, and more particularly, to a method for measuring on resistance in an H-bridge.
An H-bridge (also referred to as a full bridge), which is formed by four transistors, is known as a driver for driving a motor. Nowadays, devices have become smaller and consume less power. This has reduced the size of the transistors used in drivers such as in H-bridges. To ensure the operation of an H-bridge, the performance of the transistors must be tested and accurately evaluated. However, to drive a motor with high efficiency, the on resistance of the transistors used in an H-bridge is particularly small. This presents difficulties when measuring the on resistance of the transistors.
FIG. 1 is a schematic circuit diagram illustrating a prior art process for measuring the on resistance in an H-bridge 10. The H-bridge 10 includes first to fourth transistors T1, T2, T3, and T4, each formed by an NMOS transistor. The drains of the first and third transistors T1 and T3 are connected to a high power supply terminal VM, and the sources of the second and fourth transistors T2 and T4 are connected to a low power supply terminal (ground) PGND. The first and second transistors T1 and T2 are connected in series, with a node therebetween connected to a first output terminal OUTA. In the same manner, the third and fourth transistors T3 and T4 are connected in series, with a node therebetween connected to a second output terminal OUTB. During operation of the H-bridge 10, the first and second output terminals OUTA and OUTB are connected to a motor (not shown). Drive signals S1 and S2 respectively drive the first and second transistors T1 and T2 in a complementary manner, and drive signals S3 and S4 respectively drive the third and fourth transistors T3 and T4 in a complementary manner. When the first transistor T1 is activated, the fourth transistor T4 is activated. In this case, high power supply voltage is output to the first output terminal OUTA, and ground voltage is output to the second output terminal OUTB. When the second transistor T2 is activated, the third transistor T3 is activated. In this case, ground voltage is output to the first output terminal OUTA, and high power supply voltage is output to the second output terminal OUTB. Accordingly, the H-bridge 10 is controllable of the forward turning and reverse turning of the motor.
Automatic test equipment (“ATE”) 20, which conducts four-wire measurement, or the so-called Kelvin measurement, is used to measure the on resistance of the H-bridge 10. The ATE 20 includes a test board (not shown) including an IC socket. The IC socket holds an IC, which includes the H-bridge 10. The high power supply terminal VM is supplied with operational voltage VDD. In the prior art, for example, when measuring the on resistance of the third transistor T3, a current source 22 for supplying measurement current I1 is connected between the terminals OUTB and PGND. The ATE 20 measures the voltage V1 at the high voltage terminal VM with a voltmeter 24 connected between the terminals VM and PGND and measures the voltage V2 at the second output terminal OUTB with a voltmeter 26 connected between the terminals OUTB and PGND. The ATE 20 obtains the on resistance of the third transistor T3 based on the measurement voltages V1 and V2 and the measurement current I1. By changing the connection positions of the current source 22 and the voltmeters 24 and 26, the on resistances of the other transistors T1, T2, and T4 can be measured in the same manner.
However, the measuring process of the prior art has a shortcoming in that measurement errors are produced. The measurement errors are produced due to contact resistance between the IC socket and the tested IC (here, the terminals VM, PGND, OUTA, and OUTB) and the resistance of the wiring on the test board from the Kelvin connection point (connection positions of the current source 22 and the voltmeters 24 and 26). For example, in the case shown in FIG. 1, the voltage V1 measured by the voltmeter 24 includes a voltage drop value caused by the contact resistance between the terminals VM and PGND and the wiring resistance between these terminals. In the same manner, the voltage V2 measured by the voltmeter 26 includes a voltage drop value caused by the contact resistance between the terminals OUTB and PGND and the wiring resistance between these terminals. Additionally, if the terminals VM, PGND, OUTA, and OUTB are flawed due to a scratch or dust, variations occur in the contact resistance. Accordingly, the voltages V1 and V2 include errors caused by the voltage drop. As the transistor becomes smaller, the on resistance also becomes smaller. Thus, during the on resistance measurement, the influence of the contact resistance and wiring resistance cannot be ignored.
Japanese Laid-Open Patent Publication No. 2005-77322 describes conducting the Kelvin measurement by contacting a single electrode pad of a semiconductor element with two needles to reduce the contact resistance. However, the electrode pad of a semiconductor element is small. Thus, the testing is difficult since the two needles may fall off from the small electrode pad. Further, the technique of the publication increases the number of pins used in a tester.